Functional Verification Engineer
- Experience in pre-silicon Verification based on digital and analog/mixed signal designs.
- Bachelor’s or Masters degree in Electrical Engineering, Communications or an equivalent university program.
- In depth knowledge of HVL (Hardware verification Language) like SystemVerilog, ‘e’ and experience in building verification environments using UVM methodology .
- Domain Knowledge of Ethernet L2/L3 Switching concepts and deep understanding of Ethernet protocol is a plus.
- Functional Safety of systems/IPs - ISO 26262 experience is an added advantage.
- Applying Metric driven Verification experience in projects is key.
UPF 2.0 power aware simulations knowledge desired.
- Creating Designs using RTL (Verilog, VHDL, SystemVerilog) is a plus.
- Development of testbench concept and testbench architecture.
- Excellent design debug and root causing capabilities would be preferred.
- Knowledge of UNIX/Linux based scripting Languages like Perl or Python.
- Able to abstract technical details. Open to communicate with people on and off site. Open-minded.
- Excellent communication skills, enjoys working in an international team across locations
- Very good level of spoken and written English ( at least B2 level).
- Strong presentation and listening skills are required
- Team player
- Self-driven and highly motivated
- Good problem solving skills
- Good organizational skills and quality awareness
- Opportunity to work for a stable and expanding German company with a mature and technically involved management
- Excellent working environment, encouraging both technical and personal involvement
- Work together with a team of 70+ senior experts across multiple expertise domains in a global team setup
- Strategic partnerships with leading semiconductor companies.
- Transparent yearly bonus system